1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly to a process for forming nonvolatile programmable read-only memories including a plurality of series arrays of memory cells.
2. Description of the Related Art
Recently, in the field of programmable read-only memories (EPROMs), specific EEPROMs have been proposed which include an array of memory cells in rows and columns that are subdivided into a plurality of series circuits of memory cells in order to fulfill the ever-growing demand of further improvement in the integration density. The EPROMs of this type are called "NAND cell type EEPROMs," a typical one of which is disclosed in U.S. Pat. No. 4,939,690 to Momodomi et al. entitled "Electrically Erasable Programmable Read-Only Memory with NAND Cell Structure That Suppresses Memory Cell Threshold Voltage Variation" and assigned to the assignee of the present patent application. With the disclosed arrangement, each memory cell is constituted by only one transistor, maximizing the packing density of memory cells on a chip substrate.
There is no end to the ever-growing demand of higher integration of semiconductor memory devices. This is also true with EPROMs. In the fabrication of semiconductor memories such as EPROMs, miniaturization of device geometry has been an important goal not only to provide minimized device size, but also to improve certain device performance characteristics, such as operating speed. Particularly, in NAND cell type EEPROMs, it is a shortcut for dramatic density improvement to narrow the interval between adjoining memory cell transistors in each series array of memory cell transistors.
Unfortunately, the interval between neighboring memory cell transistors depends on the fabrication precision of the currently available patterning technique. In other words, the pitch of the memory cell transistors cannot be expected to be made narrower than the limit allowed by the existing patterning technique. The presence of any wasted space between the cell transistors is a significant impediment to the packing density improvement in the memory cells in EEPROMs. Employing a special patterning technique may improve the memory packing density at the significant risk of reducing the manufacturing yield to semiconductor manufacturers. It is therefore a general speculation that satisfying the demand of higher integration while breaking through the lowest pitch patternable with the presently available fabricating technique is substantially impossible.